The memory controller of typical computer systems communicates with memory [e.g. dynamic random access memory (DRAM)] circuits that are positioned on dual inline memory modules (DIMMs). A set of signal lines, collectively referred to as a memory bus or memory channel, is used to connect the memory controller to one or more DIMMs. The memory bus typically includes a data bus, an address bus, a control bus, and clock signals. In a parallel memory bus topology, the memory bus connects to a plurality of DIMMs in parallel.
Each DIMM in a parallel memory bus topology connects to all the data signals, all the address signals, and some or all of the control and clock signals of the memory bus. Thus, the data bus width of a DIMM matches that of the memory bus. However, the number of data I/O signals of a DRAM circuit is usually smaller than the number of data I/O signals of a DIMM. In other words, the data bus width of a DRAM circuit is smaller than the data bus width of a DIMM. Therefore, a plurality of DRAM circuits are operated in parallel to match the data widths of the individual DRAM circuits to that of the DIMM. The plurality of DRAM circuits that are controlled by a common control signal (e.g. a chip select signal) and respond in parallel to an access from the memory controller are referred to as a rank of DRAM circuits. DIMMs with one and two ranks are commonly available.
In a parallel memory bus topology, the impedance discontinuity and the bus loading caused by a DIMM affects the signal integrity of the memory bus. Consequently, as the frequency of operation of the memory bus increases, the maximum number of DIMMs that can be supported by a memory bus decreases. For example, at a 533 MHz data rate, four DIMMs per channel are feasible. However, it is expected that only two DIMMs per channel may be feasible at a 1333 MHz data rate. Thus, computer system designers are increasingly being forced to choose between memory bandwidth and memory capacity.
There is thus a need for addressing these and/or other issues associated with the prior art.
A system is provided for multi-rank, partial width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.